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? semiconductor components industries, llc, 2006 march, 2006 ? rev. 4 1 publication order number: ncp5007/d ncp5007 compact backlight led boost driver the ncp5007 is a high efficiency boost converter operating in a current control loop, based on a pfm mode, to drive white leds. the current mode regulation allows a uniform brightness of the leds. the chip has been optimized for small ceramic capacitors and is capable of supplying up to 1.0 w output power. features ? inductor based converter brings high efficiency ? constant output current regulation ? 2.7 to 5.5 v input voltage range ? v out to 22 v output compliance allows up to 5 leds to be driven in series which provides automatic led current matching ? built?in output overvoltage protection ? 0.3 a standby quiescent current ? includes dimming function (pwm) ? enable function driven directly from low battery voltage source ? thermal shutdown protection ? all pins are fully esd protected ? low emi radiation ? pb?free package is available typical applications ? led display back light control ? high efficiency step up converter figure 1. typical application gnd en 2 4 5 v out v bat ncp5007 l1 22 h v bat c1 4.7 f gnd d6 d5 d4 d3 u1 3 d2 v bat gnd 1 gnd r1 5.6 d1 mbr0530 gnd c2 1.0 f fb tsop?5 (sot23?5, scr59?5) sn suffix case 483 http://onsemi.com marking diagram dcl = device code a = assembly location y = year w = work week = pb?free package 1 5 dclayw 5 4 1 2 3 pin connections fb gnd en v bat v out (top view) 1 5 device package shipping ? ordering information ncp5007snt1 tsop?5 3000/tape & ree l ncp5007snt1g tsop?5 (pb?free) 3000/tape & ree l ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. (note: microdot may be in either location)
ncp5007 http://onsemi.com 2 figure 2. block diagram v bat v bat controller gnd q1 +200 mv 100 k en gnd gnd thermal shutdown 3 current sense vsense 2 5 v out 4 band gap + ? 1 fb 300 k
ncp5007 http://onsemi.com 3 pin function description pin symbol type description 1 fb analog input this pin provides the output current range adjustment by means of a sense resistor connected to the analog control or with a pwm control. the dimming function can be achieved by applying a pwm voltage technique to this pin (see figure 29). the current output tolerance depends upon the accuracy of this resistor. using a 5% metal film resistor, or better, yields good output current accuracy. note: a built?in comparator switches off the dc?dc converter if the voltage sensed across this pin and ground is higher than 700 mv typical. 2 gnd power this pin is the system ground for the ncp5007 and carries both the power and the analog signals. high quality ground must be provided to avoid spikes and/or uncontrolled operation. care must be observed to avoid high?density current flow in a limited pcb copper track so a robust ground plane connection is recommended. 3 en digital input this is an active?high logic input which enables the boost converter. the built?in pulldown resistor disables the device when the en pin is left open. note the logic switching level of this input has been optimized to allow it to be driven from standard or 1.8 v cmos logic levels. the led brightness can be controlled by applying a pulse width modulated signal to the enable pin (see figure 30). 4 v out power this pin is the power side of the external inductor and must be connected to the external schottky diode. it provides the output current to the load. since the boost converter operates in a current loop mode, the output voltage can range up to +22 v but shall not exceed this limit. however, if the voltage on this pin is higher than the ovp threshold (over voltage protection) the device enters a shutdown mode. to restart the chip, one must either apply a low to high logic signal to the en pin, or switch off the v bat supply. a capacitor must be used on v out to avoid false triggering of the ovp (overvoltage protect) circuit. this capacitor filters the noise created by the fast switching transients. in order to limit the inrush current and still have acceptable startup time the capacitor value should range between 1.0 f and 8.2 f max. to achieve high efficiency this capacitor should be ceramic (esr 100 m ). care must be observed to avoid emi through the pcb copper tracks connected to this pin. 5 v bat power the external voltage supply is connected to this pin. a high quality reservoir capacitor must be connected across pin 5 and ground to achieve the specified output voltage parameters. a 4.7 f/6.3 v, low esr capacitor must be connected as close as possible across pin 5 and ground pin 2. the x5r or x7r ceramic murata types are recommended. the return side of the external inductor shall be connected to this pin. typical application will use a 22 h, size 1210, to handle the 10 to 100 ma output current range. when the desired output current is above 20 ma, the inductor shall have an esr 1.5 to achieve good efficiency over the v bat range . the output current tolerance can be improved by using a larger inductor value.
ncp5007 http://onsemi.com 4 maximum ratings rating symbol value unit power supply v bat 6.0 v output power supply voltage compliance v out 28 v digital input voltage digital input current en ?0.3 v in v bat +0.3 1.0 v ma esd capability (note 1) human body model (hbm) machine model (mm) v esd 2.0 200 kv v tsop5 package power dissipation @ t a = +85 c (note 2) thermal resistance, junction?to?air p d r ja 160 250 mw c/w operating ambient temperature range t a ?25 to +85 c operating junction temperature range t j ?25 to +125 c maximum junction temperature t jmax +150 c storage temperature range t stg ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds the following tests: human body model (hbm) 2.0 kv per jedec standard: jesd22?a114 machine model (mm) 200 v per jedec standard: jesd22?a115 2. the maximum package power dissipation limit must not be exceeded. 3. latchup current maximum rating: 100 ma per jedec standard: jesd78. 4. moisture sensivity level (msl): 1 per ipc/jedec standard: j?std?020a. power supply section (typical values are referenced to t a = +25 c, min & max values are referenced ?25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit power supply 4 v bat 2.7 ? 5.5 v output load voltage compliance 5 v out 22 24.5 ? v continuous dc current in the load @ v out = 3 led, l = 22 h, esr < 1.5 , v bat = 3.6 v 5 i out 50 ? ? ma standby current @ i out = 0 ma, en = l, v bat = 3.6 v 4 i stdb ? 0.45 ? a standby current @ i out = 0 ma, en = l, v bat = 5.5 v 4 i stdb ? 1.0 3.0 a inductor discharging time @ v bat = 3.6 v, l = 22 h, 3 led, i out = 10 ma 4 toffmax ? 320 ? ns thermal shutdown protection ? t sd ? 160 ? c thermal shutdown protection hysteresis ? t sdh ? 30 ? c
ncp5007 http://onsemi.com 5 analog section (typical values are referenced to t a = +25 c, min & max values are referenced ?25 c to +85 c ambient temperature, unless otherwise noted.) rating pin symbol min typ max unit high level input voltage low level input voltage 1 en 1.3 ? ? ? ? 0.4 v en pull down resistor 1 r en ? 100 ? k feedback voltage threshold 4 fb 170 200 230 mv output current stabilizes @ 5% time delay following a dc?dc startup @ v bat = 3.6 v, l = 22 h, i out = 20 ma 5 i outdly ? 100 ? s internal switch on resistor @ t amb = +25 c 5 qr dson ? 1.7 ? 5. the overall tolerance depends upon the accuracy of the external resistor. theory of operation the dc?dc converter is designed to supply a constant current to the external load, the circuit being powered from a standard battery supply. since the regulation is made by means of a current loop, the output voltage will vary depending upon the dynamic impedance presented by the load. considering a high intensity led, the output voltage can range from a low of 6.4 v (two led in series biased with a low current), up to 22 v, the maximum the chip can sustain continuously. the basic dc?dc structure is depicted in figure 3. with a 22 v operating voltage capability, the power device q1 can accommodate a high voltage source without any leakage current degradation. por logic control time_out zero_crossing reset gnd vdsense q1 vds l1 22 h v bat d1 c2 d5 d4 d3 d2 gnd vs r2 xr gnd r1 c2 + ? gnd vref v(ipeak) + ? vdsense figure 3. basic dc?dc converter structure 4 1 1.0 f
ncp5007 http://onsemi.com 6 basically, the chip operates with two cycles: cycle #1 : time t1, the energy is stored into the inductor cycle #2 : time t2, the energy is dumped to the load the por signal sets the flip?flop and the first cycle takes place. when the current hits the peak value, defined by the error amplifier associated with the loop regulation, the flip?flop resets, the nmos is deactivated and the current is dumped into the load. since the timing is application dependent, the internal timer limits the toff cycle to 320 ns (typical), making sure the system operates in a continuous mode to maximize the energy transfer. figure 4. basic dc?dc operation first startup normal operation i l 0 ma ids 0 ma io 0 ma iv ipeak t t t t1 t2 based on the data sheet, the current flowing into the inductor is bounded by two limits: ? ipeak value: internally fixed to 350 ma typical ? iv value: limited by the fixed toff time built in the chip (320 ns typical) the system operates in a continuous mode as depicted in figure 4 and t 1 & t 2 times can be derived from basic equations. (note: the equations are for theoretical analysis only, they do not include the losses.) e l* di dt (eq. 1) let e = v bat , then: t1 (ip iv) * l vbat (eq. 2) t2 (ip iv) * l vo vbat (eq. 3) since t 2 = 320 ns typical and vo = 22 v maximum, then (assuming a typical v bat = 3.0 v): i t2 * (vo vbat) l (eq. 4) imax 320e 9 *(22 3.0) 22e 6 276 ma of course, from a practical stand point, the inductor must be sized to cope with the peak current present in the circuit to avoid saturation of the core. on top of that, the ferrite material shall be capable to operate at high frequency (1.0 mhz) to minimize the foucault?s losses developed during the cycles. the operating frequency can be derived from the electrical parameters. let v = vo ? v bat , rearranging equation 1: ton di * l e (eq. 5) since toff is nearly constant (according to the 320 ns typical time), the di is constant for a given load and inductance value. rearranging equation 5 yields: ton v*dt l *l e (eq. 6) let e = v bat , and vopk = output peak voltage, then: ton (vopk vbat) * dt vbat (eq. 7) finally, the operating frequency is: f 1 ton toff (eq. 8) the output power supplied by the ncp5007 is limited to one watt: figure 5 shows the maximum power that can be delivered by the chip as a function of the input voltage.
ncp5007 http://onsemi.com 7 1200 6 400 5 3 p out (mw) 0 v bat (v) 200 800 1000 600 24 p out = f(v bat ) @ r sense = 2.0 2 led 3 led 5 led 4 led 120 40 i out (ma) 0 v bat (v) 20 80 100 60 3.0 4.0 5.0 2.5 3.5 4.5 5.5 figure 5. maximum output power as a function of the battery supply voltage figure 6. typical inductor peak current as a function of v bat voltage figure 7. maximum output current as a function of v bat 350 4 3 2 ipeak (ma) 150 400 v bat (v) 200 300 5 250 6 l = 22 h r sense = 10 t a = +25 c test conditions: 5 leds in series, steady state operation test conditions: l = 22 h, rsense = 2.0 , tamb = +25 c 2 led 3 led 4 led 5 led
ncp5007 http://onsemi.com 8 output current range set?up the current regulation is achieved by means of an external sense resistor connected in series with the led string. controller gnd 1 fb gnd 4 v out d1 load q1 figure 8. output current feedback v bat l1 22 h r1 x the current flowing through the led creates a voltage drop across the sense resistor r1. the voltage drop is constantly monitored internally, and maximum peak current allowed in the inductor is set accordingly in order to keep constant this voltage drop (and thus the current flowing through the led). for example, should one need a 10 ma output current, the sense resistor should be sized according to the following equation: r 1 feedback threshold i out 200 mv 10 ma 20 (eq. 9) a standard 5% tolerance resistor, 22 smd device, yields 9.09 ma, good enough to fulfill the back light demand. the typical application schematic diagram is provided in figure 9. figure 9. basic schematic diagram gnd en 2 4 5 v out v bat ncp5007 l1 22 h v bat c1 4.7 f gnd d6 d5 d4 d3 u1 3 d2 gnd 1 gnd r1 22 d1 mbr0530 gnd c2 1.0 f fb pulse led led led led led
ncp5007 http://onsemi.com 9 output load drive in order to take advantage of the built?in boost capabilities, one shall operate the ncp5007 in the continuous output current mode. such a mode is achieved by using and external reservoir capacitor (see table 1) across the led. at this point, the peak current flowing into the led diodes shall be within the maximum ratings specified for these devices. of course, pulsed operation can be achieved, thanks to the en signal pin 3, to force high current into the led when necessary. the schottky diode d1, associated with capacitor c2 (see figure 9), provides a rectification and filtering function. when a pulse?operating mode is required: ? a pwm mode control can be used to adjust the output current range by means of a resistor and a capacitor connected across fb pin. on the other hand, the schottky diode can be removed and replaced by at least one led diode, keeping in mind such led shall sustain the large pulsed peak current during the operation. typical operating characteristics 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) efficiency (%) 5 led/10 ma 3 led/10 ma 4 led/10 ma 2 led/10 ma 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) efficiency (%) 5 led/4 ma 3 led/4 ma 4 led/4 ma 2 led/4 ma figure 10. overall efficiency vs. power supply ? i out = 4.0 ma, l = 22 h figure 11. overall efficiency vs. power supply ? i out = 10 ma, l = 22 h 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) efficiency (%) 5 led/20 ma 3 led/20 ma 4 led/20 ma 2 led/20 ma 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vbat (v) efficiency (%) 5 led/15 ma 3 led/15 ma 4 led/15 ma 2 led/15 ma figure 12. overall efficiency vs. power supply ? i out = 15 ma, l = 22 h figure 13. overall efficiency vs. power supply ? i out = 20 ma, l = 22 h
ncp5007 http://onsemi.com 10 figure 14. overall efficiency vs. power supply ? i out = 40 ma, l = 22 h figure 15. current variation vs. power supply wit h 3 series led?s figure 16. current variation vs. power supply with 4 series led?s figure 17. current variation vs. power supply with 5 series led?s figure 18. feedback voltage stability typical operating characteristics efficiency (%) v bat (v) 205 200 feedback voltage (mv) 195 temperature ( c) 199 202 203 201 0 20 100 198 197 196 ?40 40 ?20 60 80 204 5 0 feedback variation (%) ?5 temperature ( c) ?1 2 3 1 0 20 100 ?2 ?3 ?4 ?40 40 ?20 60 80 4 v bat = 3.1v thru 5.5v 30 15 2.5 i out (ma) 0 v bat (v) 25 3.0 5.0 10 4.0 4.5 i out = 10 ma nom l = 22 h t a = 25 c 3.5 v bat = 3.1 v thru 5.5 v (all curve conditions: l = 22 h, cin = 4.7 f, c out = 1.0 f, typical curve @ t a = +25 c) figure 19. feedback voltage variation 0 10 20 30 40 50 60 70 80 90 100 2.50 3.00 3.50 4.00 4.50 5.00 5.50 5 led/40 ma 3 led/40 ma 4 led/40 ma 2 led/40 ma 5.5 20 5 i out = 20 ma nom 25 15 2.5 i out (ma) 0 v bat (v) 3.0 5.0 10 4.0 4.5 i out = 10 ma nom l = 22 h t a = 25 c 3.5 5.5 20 5 i out = 20 ma nom 25 15 2.5 i out (ma) 0 v bat (v) 3.0 5.0 10 4.0 4.5 i out = 10 ma nom l = 22 h t a = 25 c 3.5 5.5 20 5 i out = 20 ma nom
ncp5007 http://onsemi.com 11 4 led 5 led figure 20. standby current figure 21. typical operating frequency figure 22. overvoltage protection typical operating characteristics 1.4 2.7 istby ( a) 0.0 v bat , battery voltage (v) 0.6 1.0 0.8 5.5 0.4 0.2 1.2 ?40 c thru 125 c 3.3 3.9 4.5 5.1 26 24 ?40 over voltage protection (v) 22 temperature( c) 25 0 100 23 40 80 v bat = 5.5v v bat = 2.7v v bat = 3.6v 20 130 (all curve conditions: l = 22 h, cin = 4.7 f, c out = 1.0 f, typical curve @ t a = +25 c) 0 0.5 1.0 1.5 2.0 2.5 2.5 3.0 3.5 4.0 4.5 5.0 5 .5 2 led f (mhz) v bat (v) 3 led ?20 60 120
ncp5007 http://onsemi.com 12 figure 23. typical power up response figure 24. typical startup inductor current and output voltage typical operating waveforms conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma inductor current v out v out inductor current
ncp5007 http://onsemi.com 13 figure 25. typical inductor current figure 26. typical output voltage ripple typical operating waveforms conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma conditions: v bat = 3.6 v, l out = 22 h, 5 led, i out = 15 ma inductor current inductor current v out ripple 50 mv/div
ncp5007 http://onsemi.com 14 figure 27. typical output peak voltage typical operating waveforms test conditions: l = 22 h, i out = 15 ma, v bat = 3.6 v, ambient temperature, led = 5 output voltage inductor current
ncp5007 http://onsemi.com 15 typical applications circuits standard feedback the standard feedback provides constant current to the leds, independently of the v bat supply and number of leds in series. figure 28 depicts a typical application to supply 13 ma to the load. figure 28. basic dc current mode operation with analog feedback en 4 5 v out v bat r1 ncp5007 l1 22 h v bat c1 4.7 f d6 d5 d4 d3 u1 3 d2 v bat 2 gnd gnd fb 1 d1 mbr0530 15 gnd gnd c2 1.0 f led led led led led gnd pwm operation the analog feedback pin 1 provides a way to dim the led by means of an external pwm signal as depicted in figure 29. t aking advantage of the high internal impedance presented by the fb pin, one can set up a simple r/c network to accommodate such a dimming function. two modes of operation can be considered: ? pulsed mode, with no filtering ? averaged mode with filtering capacitor although the pulsed mode will provide a good dimming function, it will yield high switching transients which are difficult to filter out in the control loop. as such this first approach is not recommended. the output current depends upon the duty cycle of the signal presented to the node pin 1: this is very similar to the digital control shown in figure 30. the average mode yields a noise?free operation since the converter operates continuously, together with a very good dimming function. the cost is an extra resistor and one extra capacitor, both being low cost parts.
ncp5007 http://onsemi.com 16 figure 29. basic dc current mode operation with pwm control en 4 5 v out v bat r1 ncp5007 l1 22 h v bat c1 4.7 f d6 d5 d4 d3 u1 3 d2 v bat 2 gnd gnd fb 1 d1 mbr0530 10 gnd gnd c2 1.0 f led led led led led r4 5.6 k r3 10 k gnd c3 100 nf sense resistor r2 150 k pwm average network note: rc filter r2 and c3 is optional (see text) gnd to implement such a functi on, lets consider the feedback input as an operational amplifier with a high impedance input (reference schematic figure 29). the analog loop will keep going to balance the current flowing through the sense resistor r1 until the feedback voltage is 200 mv. an extra resistor (r4) isolates the fb node from low resistance to ground, making possible to add an external voltage to this pin. the time constant r2/c3 generates the voltage across c3, added to the node pin 1, while r2/r3/r4/r1/c3 create the discharge time constant. in order to minimize the pick up noise at fb node, the resistors shall have relative medium value, preferably well below 1.0 m . consequently, let r2 = 150 k, r3 = 10 k and r4 = 5.6 k. in addition, the feedback delay to control the luminosity of the led shall be acceptable by the user, 10 ms or less being a good compromise. the time constant can now be calculated based on a 400 mv offset voltage at the c3/r2/r3 node to force zero current to the led. assuming the pwm signal comes from a standard gate powered by a 3.0 v supply, running at 5.0 khz, then full dimming of the led can be achieved with a 95% span of the duty cycle signal. digital control an alternative method of controlling the luminosity of the leds is to apply a pwm signal to the en pin (see figure 30). the output current depends upon the duty cycle, but care must be observed as the dc?dc converter is continuously pulsed on/off and noise is likely to be generated. figure 30. typical semi?pulsed mode of operation en 4 5 v out v bat r1 ncp5007 l1 22 h v bat c1 4.7 f gnd d6 d5 d4 d3 u1 3 d2 2 gnd gnd fb 1 d1 mbr0530 5.6 gnd gnd pulse c2 1.0 f note: pulse width and frequency depends upon the application constraints.
ncp5007 http://onsemi.com 17 typical leds load mapping since the output power is battery limited (see figure 5), one can arrange the leds in a variety of different configurations. powering ten leds can be achieved by a series/parallel combination as depicted in figure 31. figure 31. examples of possible led arrangements d1 led d2 led d3 led d4 led d5 led d6 led d7 led d8 led d9 led d10 led load 75 ma 7.0 v (typ.) d1 led d2 led d3 led d4 led load 50 ma 14 v (typ.) d1 led d2 led load 60 ma 10.5 v (typ.) d3 led d4 led d5 led d6 led d7 led d8 led d9 led d5 led d6 led d7 led d8 led d10 led d11 led d12 led d13 led d14 led d15 led gnd r1 3.9 sense resistor test conditions: v bat = 3.6 v l out = 22 h c out = 1.0 f gnd r1 2.7 sense resistor gnd r1 3.3 sense resistor
ncp5007 http://onsemi.com 18 on semiconductor provides a demo board to evaluate the performance of the ncp5007. the schematic for that demo board is illustrated in figure 32. figure 32. ncp5007 demo board schematic diagram en 5 v out v bat ncp5007 l1 22 h v bat c1 4.7 f/10 v d6 d5 d4 d3 u1 3 d2 2 gnd gnd fb 1 d1 mbr0530 led led led led led r2 10 k gnd jp1 isense 4 tp1 v out c3 gnd tp3 v bat 2 1 3 s2 select 2 1 3 s1 manual 2 1 3 s3 brightness r5 0 r gnd r3 10 k jumper = 0 modulation r1 150 k gnd j3 tp2 fb r4 5.6 k gnd c2 100 nf 2 1 v bat j2 pwr 1 2 j1 v bat gnd z1 r10 10 r v bat
ncp5007 http://onsemi.com 19 table 1. recommended external parts part manufacturer description part number 30 v low vf schottky diode on semiconductor sod?123 (1.6 x 3.2 mm) mbr0530t1 20 v low vf schottky diode on semiconductor sod?323 (1.25 x 2.5 mm) nsr0320mw2t1 20 v low vf schottky diode on semiconductor sod?563 (1.6 x 1.6 mm) nsr0320xv6t1 ceramic cap. 1.0 f/16 v murata grm42?x7r grm42?6x7r?105k16 ceramic cap. 4.7 f/6.3 v murata grm40?x5r grm40?x5r?475k6.3 inductor 22 h coilcraft 1008ps?shielded 1008ps?223mc inductor 22 h coilcraft power wafer lpq4812?223kxc figure 33. ncp5007 demo board pcb: top layer figure 34. ncp5007 demo board top silkscreen
ncp5007 http://onsemi.com 20 figures index figure 1: typical application 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 2: block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 3: basic dc?dc converter structure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 4: basic dc?dc operation 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 5: maximum output power as a function of the battery supply voltage 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 6: typical inductor peak current as a function of v bat voltage 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 7: maximum output current as a function of v bat 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 8: output current feedback 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 9: basic schematic diagram 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 10: overall efficiency vs. power supply ? i out = 4.0 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 11: overall efficiency vs. power supply ? i out = 10 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 12: overall efficiency vs. power supply ? i out = 15 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 13: overall efficiency vs. power supply ? i out = 20 ma, l = 22 h9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 14: overall efficiency vs. power supply ? i out = 40 ma, l = 22 h10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 15: feedback voltage stability 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 16: feedback voltage variation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 17: standby current 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 18: typical operating frequency 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 19: overvoltage protection 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 23: typical power up response 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 24: typical startup inductor current and output voltage 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 25: typical inductor current 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 26: typical output voltage ripple 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 27: typical output peak voltage 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 28: basic dc current mode operation with analog feedback 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 29: basic dc current mode operation with pwm control 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 30: typical semi?pulsed mode of operation 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 31: examples of possible led arrangements 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 32: ncp5007 demo board schematic diagram 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 33: ncp5007 demo board pcb: top layer 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . figure 34: ncp5007 demo board top silkscreen 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note captions index note 1: this device series contains esd protection and exceeds the following tests 4 . . . . . . . . . . . . . . . . . . . . . . . . . . note 2: the maximum package power dissipation limit must not be exceeded 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . note 3: latchup current maximum rating: 100 ma per jedec standard: jesd78 4 . . . . . . . . . . . . . . . . . . . . . . . . . note 4: moisture sensivity level (msl): 1 per ipc/jedec standard: j?std?020a 4 . . . . . . . . . . . . . . . . . . . . . . . . . note 5: the overall tolerance depends upon the accuracy of the external resistor 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . abbreviations en enable fb feed back por power on reset: internal pulse to reset the chip when the power supply is applied
ncp5007 http://onsemi.com 21 package dimensions tsop?5 sn suffix case 483?02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. a and b dimensions do not include mold flash, protrusions, or gate burrs. dim min max min max inches millimeters a 2.90 3.10 0.1142 0.1220 b 1.30 1.70 0.0512 0.0669 c 0.90 1.10 0.0354 0.0433 d 0.25 0.50 0.0098 0.0197 g 0.85 1.05 0.0335 0.0413 h 0.013 0.100 0.0005 0.0040 j 0.10 0.26 0.0040 0.0102 k 0.20 0.60 0.0079 0.0236 l 1.25 1.55 0.0493 0.0610 m 0 10 0 10 s 2.50 3.00 0.0985 0.1181 0.05 (0.002) 123 54 s a g l b d h c k m j __ _ _ 0.7 0.028 1.0 0.039 mm inches
scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 ncp5007/d literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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